1. Field of the Invention
This invention relates to a process and equipment for making patterned metal structures on insulating substrates, and more particularly to forming desired electrical interconnections on printed circuit boards and substrates for interconnecting microelectronic circuits. It comprises a voltage ramping process followed by a current ramping process of alternating current electrical power into a partially formed metal structure immersed in a plating solution, to provide local Joule heating at the weak links in the metal structure, thus to induce local electrolytic plating or local electroless plating onto the weak links.
2. Description of the Prior Art
In addition to the lithographic method (parallel process), the customized wiring process (serial process) is an important manufacturing step in the microelectronics industry. First, almost in any practical case of complicated microelectronics system, customized interconnections have to be made after the lithography step, which is called engineering changes (EC). Second, the printed circuit boards and modules manufactured from lithography often have defects. The circuit opens are the most common one. Traditionally, the circuit opens are repaired by ribbon brazing. As the dimensions of microelectronic units becomes smaller and smaller, the ribbon brazing method becomes impractical. The EC's often have complicated geometry and the ribbon brazing method cannot be applied. Laser chemical vapor deposition (LCVD) has been considered as a leading technology for making open repair and EC's. LCVD has been described in U.S. Pat. No. 4,340,617 which issued on Jul. 20, 1982 to Deutsch et al. entitled "Method and Apparatus for Depositing a Material on a Surface" and in U.S. Pat. No. 4,615,904 which issued on Oct. 7, 1986 to Ehrlich et al. entitled "Maskless Growth of Patterned Films." However, there are several problems with the LCVD method: the resistivity of LCVD deposited metal is usually much higher than the bulk due to the porous structure and inclusion of organic materials; the contact resistance between the original line and the LCVD deposition is often too high; the deposition process requires a good vacuum, but the outgassing of the substrate can take up to several hours; and finally, for large circuit boards, the atmospheric pressure on the optical window of the vacuum chamber can be as high as a few metric tons, a severe structural and optical problem for the apparatus.
In a publication by M. E. Gross et al., entitled "Laser Direct-Write Metallization in Thin Palladium Acetate Films", J. Appl. Phys. 61, 1628 (1987), a system for deposition of palladium from a single component metal-organic film or palladium acetate which was spin coated from a chloroform solution was described. Decomposition of the film was induced by a focused 20 watt cw argon laser wherein the film coating was 0.1 to 1.5 .mu.m thick. However, the resistance of the palladium interconnection thus generated, usually between a few ohms and a few kilohms, is too high to be useful in microelectronics circuits.
A novel method for repairing circuit defects has been described in U.S. Pat. No. 4,919,971 which issued on Apr. 24, 1990 to C. J. Chen entitled "Self-Induced Repairing of Conductor Lines" and assigned to the assignee herein. For treating a circuit line with a near open (constriction), the printed circuit board is immersed in a plating solution. An ac current is passed through the defective line. Because the defect (near open, constriction) has a higher electrical resistance and a higher thermal resistance, it becomes hotter than the normal parts of the line. Either by the thermobattery effect (in electrolytic plating solution) or by the temperature dependence of plating rate (in the electroless plating solution), the defect is plated up preferentially. The patent recites that an alternating current is preferred but that the frequency and the wave shpae are probably not critical. Further, the most convenient source to use is described as a 60 hertz commercial power line with the voltage reduced to a few volts. The patent describes the process as starting with a low AC current, for example, 1 ampere, and slowly ramping the current up with a speed of 1-2 amperes/minute until it reached 4 amperes to 4.5 amperes which was the maximum tolerable current for this conductor line. The current was maintained at 4 to 4.5 amperes for about 2-3 minutes and then terminated.
A description of a two step method for repair of "opens" in an electronic circuit is found in U.S. Pat. No. 4,994,154 which issued Feb. 19, 1991 to C. J. Chen and R. J. von Gutfeld entitled "High Frequency Electrochemical Repair of Open Circuits" and assigned to the Assignee herein. In the first repair step, the electronic material is partially covered or immersed in a plating solution and a high frequency current is passed through the open ends of the circuit with the plating solution enabling the current to complete the path. The resulting Joule losses produces heat directly proportional to the resistance of the current path, resulting in metal deposition of a few microns in width across the circuit break. The second step consists of passing alternating current through the relatively high resistant defect in a high speed plating solution. The alternating current may be low frequency of about 50 hertz or greater. The frequency of alternating current during the first step can range from about 0.04 kHz TO 5,000 kHz in contact, either submerged or covered by one or several droplets, with an unacidified neutral metal ion solution which results in a rapid growth of the metal in the gap, the open circuit. During the first step, metal deposition in the form of dendrite growth occurs at a linear rate of up to 2-5 .mu.m/s with a current (voltage) being ramped from 0 to several milliamps over the time span of the repair. Slow current ramping is normally undertaken to initiate controlled growth of the metal typically copper. The patent further describes metal probes preferably made of copper or copper alloys placed in contact with the pads or ends of a defective line. A resistor and high frequency current source constitute the electrical circuit which is used to provide alternating current.
The self-induced repair process of U.S. Pat. No. 4,919,971 can also be used for repairing true opens in conductors and for producing customized interconnections. By making an initial connection to the circuit open with a conducting film (for example, laser direct writing using an organometallic film, the situation becomes similar to a near-open. The self induced repair process then restores a near-open to a uniform metal line.
However, by directly using the self-induced repair process described in U.S. Pat. No. 4,919,971, the success rate has been low. Experiments have shown that the resistance of the seeded trace generated by laser solid-film process spreads over a wide range, from a few ohms to tens of kilohms. Using the current ramping method disclosed in U.S. Pat. No. 4,919,971, the seeded metal (e.g., palladium) trace often breaks because of excess heat.
For a process to be used as a manufacturing method, it should be very reliable, and the yield should be close to 100%. Also, the process should be ready to be automated to reduce labor cost. The present invention is an improvement of the SIR process described in U.S. Pat. No. 4,919,971. The new method can reproducibly generate high-quality interconnections with high efficiency and by nature an automated method, thus providing for high productivity.
The new control process has a number of control parameters. Those parameters depend only on the materials and the dimensions of the batch of the product, but independent to the dimension, length, width, thickness, material, and resistance of individual interconnection. Once a set of parameters for a batch of product is properly chosen, a 100% success rate is demonstrated. Moreover, by using this new method, the process time can be shortened to minimum, and the entire process can be easily made automatic, thus to reduce manufacturing cost. This process works as long as the seeded trace has a finite resistance (e.g., from a few ohms to tens of kilohms). The low requirement of the initial laser seeding makes possible the choice of a simple and inexpensive seeding step, and allows a very wide process window.